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MITSUBISHI DIGITAL ASSP MITSUBISHI DIGITAL ASSP
M66252P/FP M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO) 1152 x 8-BIT LINE MEMORY (FIFO)
DESCRIPTION The M66252P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 1152-word x 8-bit configuration which uses high-performance silicon gate CMOS process technology. It has separate clock, enable and reset signals for write and read and is most suitable as a buffer memory between devices with different data processing throughput. FEATURES * Memory construction ........................................................ ............................. 1152words x 8bits (dynamic memory) * High-speed cycle ............................................ 50ns (min.) * High-speed access ........................................ 40ns (max.) * Output hold ....................................................... 5ns (min.) * Fully independent, asynchronous write and read operations * Variable-length delay bit * Output .................................................................... 3-state APPLICATION Digital photocopiers, high-speed facsimiles, laser beam printers.
PIN CONFIGURATION (TOP VIEW)
Q0 Q1 Data output Q2 Q3 Read enable input RE Read reset input RRES GND Read clock input RCK Q4 Q5 Data output Q6 Q7
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
D0 D1 D2 D3 WE WRES VCC WCK D4 D5 D6 D7
Data input
Outline 24P4Y 24P2W-A
M66252P/FP
Write enable input Write reset input Write clock input
Data input
BLOCK DIAGRAM

D0 D1 D2 D3 D4 D5 D6 D7 24 23 22 21 16 15 14 13
Input buffer
Write reset input WRES 19 Write clock input WCK 17
Memory array (1152 x 8 bits)
Read control circuit
Write control circuit
Write enable input WE 20
Read address counter
Write address counter

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 1 2 3 4 9 10 11 12 Output buffer
Data input
Data output
5 RE Read input enable 6 RRES Read input reset 8 RCK Read input clock
Vcc 18
7 GND
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MITSUBISHI DIGITAL ASSP
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
FUNCTION When the status of write enable input WE is "L," data on D0 thru D7 are written on the memory synchronously with write clock input WCK rise edges. At this time, write address counter executes counting. The following write-related operations are also performed synchronously with WCK rise edges. When WE is "H," writing on memory is inhibited, and write address counter stops counting. When write reset input WRES is "L," write address counter is initialized.
When read enable input RE is "L," data on memory are output to Q0 thru Q7 synchronously with read clock input RCK rise edges. At this time, read address counter executes counting. The following read-related operations are also performed synchronously with RCK rise edges. When RE is "H," reading from memory is inhibited, and read address counter stops counting. The status of Q0 thru Q7 becomes high-impedance. When read reset input RRES is "L," read address counter is initialized.
ABSOLUTE MAXIMUM RATINGS (Ta = -20 ~ 70C unless otherwise noted)
Symbol VCC VI VO Pd Tstg Parameter Supply voltage Input voltage Output voltage Power dissipation Storage temperature Conditions Reference pin: GND Ta = 25C Ratings -0.5 ~ +7.0 -0.5 ~ VCC + 0.5 -0.5 ~ VCC + 0.5 550 (Note 1) -65 ~ 150 Unit V V V mW C
Note 1: Ta 62C are derated at -8.8mW/C (24P4Y) Ta 51C are derated at -7.5mW/C (24P2W)
RECOMMENDED OPERATIONAL CONDITIONS
Symbol VCC GND Topr Parameter Supply voltage Supply voltage Ambient temperature Min. 4.5 -20 Limits Typ. 5 0 Max. 5.5 70 Unit V V C
ELECTRICAL CHARACTERISTICS (Ta = -20 ~ 70C, VCC = 5V10%, GND = 0V)
Symbol VIH VIL VOH VOL IIH Parameter "H" input voltage "L" input voltage "H" output voltage "L" output voltage "H" input current Test conditions Min. 2.0 VCC - 0.8 0.55 1.0 Limits Typ. Max. 0.8 IOH = -4mA IOL = 4mA WE, WRES, WCK, RE, VI = VCC RRES, RCK D0~D7 WE, WRES, WCK, RE, VI = GND RRES, RCK D0~D7 VO = VCC VO = GND VI = VIH, VIL, Outputs are open tWCK, tRCK = 100ns f = 1MHz f = 1MHz Unit V V V V A A A A mA pF pF
IIL IOZH IOZL ICC CI CO
"L" input current "H" output current under "off" condition "L" output current under "off" condition Average supply current during operation Input capacitance Output capacitance under "off" condition
-1.0 5.0 -5.0 100 10 15
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MITSUBISHI DIGITAL ASSP
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
SWITCHING CHARACTERISTICS (Ta = -20 ~ 70C, VCC = 5V10%, GND = 0V)
Symbol tAC tOH tOEN tODIS Access time Output hold time Output enable time Output disable time Parameter Min. 5 5 5 Limits Typ. Max. 40 40 40 Unit ns ns ns ns
TIMING CHARACTERISTICS (Ta = -20 ~ 70C, VCC = 5V10%, GND = 0V)
Symbol tWCK tWCKH tWCKL tRCK tRCKH tRCKL tDS tDH tRESS tRESH tNRESS tNRESH tWES tWEH tNWES tNWEH tRES tREH tNRES tNREH tr, tf tH Parameter Write clock (WCK) cycle time Write clock (WCK) "H" pulse width Write clock (WCK) "L" pulse width Read clock (RCK) cycle time Read clock (RCK) "H" pulse width Read clock (RCK) "L" pulse width Input data setup time (in response to WCK) Input data hold time (in response to WCK) Reset setup time (in response to WCK and RCK) Reset hold time (in response to WCK and RCK) Reset non-select setup time (in response to WCK and RCK) Reset non-select hold time (in response to WCK and RCK) WE setup time (in response to WCK) WE hold time (in response to WCK) WE non-select setup time (in response to WCK) WE non-select hold time (in response to WCK) RE setup time (in response to RCK) RE hold time (in response to RCK) RE non-select setup time (in response to RCK) RE non-select hold time (in response to RCK) Input pulse rise time and fall time Data hold time (Note 1) Min. 50 25 25 50 25 25 15 5 15 5 15 5 15 5 15 5 15 5 15 5 35 20 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Note 1. The following conditions should be met for each line access: WE "H" level period 20ms - 1152 * tWCK - WRES "L" level period RE "H" level period 20ms - 1152 * tRCK - RRES "L" level period 2. Perform reset operation after turning on power supply.
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MITSUBISHI DIGITAL ASSP
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
TEST CIRCUIT
Vcc
Qn
RL=1k
CL= 30pF : tAC, tOH
SW1 Qn SW2 CL=5pF : tOEN, tODIS RL=1k
Input pulse level: 0 ~ 3V Input pulse rise time and fall time: 3ns Measurement reference level, input: 1.3V Measurement reference level, output: 1.3V (Note: tODIS (LZ) is tested at 10% output amplitude, and tODIS (HZ) is tested at 90% output amplitude.) Load capacitance CL includes floating capacitance and probe input capacitance.
Parameter tODIS(LZ) tODIS(HZ) tOEN(ZL) tOEN(ZH)
SW1 Closed Open Closed Open
SW2 Open Closed Open Closed
TEST CONDITIONS FOR OUTPUT DISABLE TIME tODIS AND OUTPUT ENABLE TIME tOEN
3V RCK 1.3V 1.3V GND
3V RE GND tODIS(HZ) 90% 1.3V tOEN(ZH) VOH
Qn
tODIS(LZ)
tOEN(ZL)
Qn
10%
1.3V VOL
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MITSUBISHI DIGITAL ASSP
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
TIMING CHARTS * Write Cycles
Cycle n
Cycle(n+1)
Cycle(n+2)
Disable cycles
Cycle(n+3)
Cycle(n+4)
WCK tWCK tWCKH tWCKL tWEH tNSES tNWEH tWES
WE
tDS tDH
tDS tDH
Dn
(n)
(n+1)
(n+2)
(n+3) WRES="H"
(n+4)
* Write Reset Cycles
Cycle(n-1)
Cycle n
Reset cycles
Cycle 0
Cycle 1
Cycle 2
WCK tWCK tNRESH tRESS tRESH tNRESS
WRES tDS tDH tDS tDH
Dn
(n -1)
(n)
(0)
(1) WE="L"
(2)
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MITSUBISHI DIGITAL ASSP
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
* Matters that needs attention when WCK stops
n cycle
n+1 cycle
n cycle
Disable cycle
WCK tWCK tNWES
WE
tDS tDH
tDS tDH
Dn
(n)
(n)
Period for writing data (n) into memory
Period for writing data (n) into memory
WRES = "H"
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of n+1 cycle. The writing operation is complete at the falling edge after n+1 cycle. To stop reading write data at n cycle, enter WCK before the rising edge after n+1 cycle. When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
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MITSUBISHI DIGITAL ASSP
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
* Read Cycles
Cycle n
Cycle(n+1)
Cycle(n+2)
Disable cycles
Cycle(n+3)
Cycle(n+4)
RCK tRCK tRCKH tRCKL tREH tNRES tNREH tRES
RE tODIS Qn (n) (n+1) (n+2)
tAC
tOEN
HIGH-Z
(n+3) tOH RRES="H"
(n+4)
* Read Reset Cycles
Cycle(n-1)
Cycle n
Reset cycles
Cycle 0
Cycle 1
Cycle 2
RCK tRCK tNRESH tRESS tRESH tNRESS
RRES
tAC
Qn
(n-1)
(n)
(0)
(0)
(0) tOH
(1)
(2)
RE="L"
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MITSUBISHI DIGITAL ASSP
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
VARIABLE-LENGTH DELAY BITS * 1-line (1152-bit) delay A write input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output from memory at the first rise edge of RCK in the cycle, so that 1-line delay can be made easily.
Cycle 0 WCK RCK tRESS tRESH WRES RRES
Cycle 1
Cycle 2
Cycle 1150
Cycle 1151
Cycle 0'
Cycle 1'
Cycle 2'
tDS tDH Dn (0) (1) (2) (1149) (1150) (1151)
tDS tDH (0') (1') (2')
1152 cycles Qn
tAC
tOH (0) (1) (2) WE, RE="L"
* n-bit delay 1 (Making a reset at a cycle corresponding to delay length)
Cycle (n-2) Cycle (n-1)
Cycle 0 WCK RCK tRESS tRESH WRES RRES
Cycle 1
Cycle 2
Cycle 0'
Cycle 1'
Cycle 2'
Cycle 3'
tRESS tRESH
tDS tDH Dn (0) (1) (2) (n-3) (n-2) (n-1)
tDS tDH (0') (1') (2') (3')
m cycles Qn
tAC
tOH (0) (1) (2) WE, RE="L" m3 (3)
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MITSUBISHI DIGITAL ASSP
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
* n-bit delay 2 (Sliding WRES and RRES at a cycle corresponding to delay length)
Cycle Cycle n(W) Cycle(n+1)(W) Cycle(n+2)(W) Cycle(n+3)(W) (n-1)(W) Cycle 0(R) Cycle 1(R) Cycle 2(R) Cycle 3(R)
Cycle 0(W) Cycle 1(W) Cycle 2(W)
WCK RCK
tRESS tRESH
WRES
tRESS tRESH
RRES
tDS tDH
tDS tDH
(1) (2) (n-2) (n-1) (n) (n+1) (n+2) (n+3)
Dn
(0)
m cycles
Qn
tAC
tDH
(0) (1) (2) (3)
WE, RE="L" m3
* n-bit delay 3 (Disabling RE at a cycle corresponding to delay length)
Cycle Cycle n(W) Cycle(n+1)(W) Cycle(n+2)(W) Cycle(n+3)(W) (n-1)(W) Cycle 0(R) Cycle 1(R) Cycle 2(R) Cycle 3(R)
Cycle 0(W) Cycle 1(W) Cycle 2(W) WCK RCK tRESS tRESH WRES RRES
tNREH tRES RE tDS tDH Dn (0) (1) (2) (n-2) (n-1) tAC tDS tDH (n) tOH (0) (1) (2) (3) WE, RE="L" m3 (n+1) (n+2) (n+3)
m cycles Qn HIGH-Z
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MITSUBISHI DIGITAL ASSP
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
* Shortest read of data "n" written in cycle n Cycle n-1 on read side should be started after end of cycle n+1 on write side When the start of cycle n-1 on read side is earlier than the end of cycle n+1 on write side, output Qn of cycle n becomes invalid. In the figure shown below, the read of cycle n-1 is invalid.
Cycle n WCK
Cycle n+1
Cycle n+2
Cycle n+3
Dn
(n)
(n + 1)
(n + 2)
(n + 3)
Cycle n - 2 RCK
Cycle n - 1
Cycle n
Qn
invalid
(n)
* Longest read of data "n" written in cycle n: 1-line delay Cycle n <1>* on read side should be started when cycle n <2>* on write is started Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1>* and the start of writing side n cycle <2>* overlap each other.
Cycle n 1 WCK
Cycle 0 2
Cycle n 2
Dn
(n - 1)1
(n)1
(0)2
(n - 1)2
(n)2
Cycle n 0 RCK
Cycle 0 1
Cycle n 1
Qn
(n - 1)0
(n)0
(0)1
(n - 1)1 0, 1 and 2 indicates a line value.
(n)1
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MITSUBISHI DIGITAL ASSP
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
APPLICATION EXAMPLE Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction.
M66252
N Line n image data
D0
Q0
~
~
Adder N+K {2N-(A+B)}
B Line (n+1) image data
D7
Q7
x2
Corrected image data
1-line delay
Subtractor 2N-(A+B)
xK
M66252 A Line (n-1) image data
D0 D7
Q0 Q7
1-line delay
Secondary scanning direction
Primary scanning direction
A N B
Line (n-1) Line n Line (n+1) N' = N+K {(N-A)+(N-B)} = N+K {2N-(A+B)} K : Laplacean coefficient
Adder A+B
~
~
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